View CY7C1471V33-133ACES_1485272.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary 72-mbit (2m x 36/4m x 18 /1m x 72) flow-through sram with nobl? architecture cy7c1471v33 cy7c1473v33 cy7c1475v33 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05288 rev. *e revised december 5, 2004 features ? no bus latency? (nobl?) architecture eliminates dead cycles between write and read cycles. ? can support up to 133-mhz bus operations with zero wait states ? data is transferred on every clock ? pin compatible and functionally equivalent to zbt? devices ? internally self-time d output buffer cont rol to eliminate the need to use oe ? registered inputs for flow-through operation ? byte write capability ? 3.3v/2.5v i/o power supply ? fast clock-to-output times ? 6.5 ns (for 133-mhz device) ? 8.5 ns (for 100-mhz device) ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous self-timed writes ? asynchronous output enable ? offered in jedec-standard lead-free 100 tqfp, and 165-ball fbga packages for cy7c1471v33 and cy7c1473v33. 209-ball fbga package for cy7c1475v33. ? three chip enables for simple depth expansion. ? automatic power-down feature available using zz mode or ce deselect. ? jtag boundary scan for bga and fbga packages ? burst capability?linear or interleaved burst order ? low standby power functional description [1] the cy7c1471v33, cy7c1473v33 and cy7c1475v33 are 3.3v, 2m x 36/4m x 18/1m x 72 synchronous flow-through burst srams designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. the cy7c1471v33, cy7c1473v33 and cy7c1475v33 are equipped with the advanced no bus latency (nobl) logic required to enable consecutive read/write operations with dat a being transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that require frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 6.5 ns (133-mhz device). write operations are controlled by the two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. in order to avoid bus contention, the output driver s are synchronously tri-stated during the data portion of a write sequence. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 335 305 ma maximum cmos standby current 150 150 ma note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com.
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 2 of 29 1 c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control logic block diagram ? cy7c1473v33 (4m x 18) c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control logic block diagram ? cy7c1471v33 (2m x 36)
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 3 of 29 a0, a1, a c mode ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d dq p e dq p f dq p g dq p h d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers bw a bw b we zz sleep control bw c write registry and data coherency control logic bw d bw e bw f bw g bw h logic block diagram ? cy7c1475v33 (1m x 72)
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 4 of 29 pin configurations 100-lead tqfp a a a a a1 a0 nc / 288m nc / 144m v ss v dd a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode a cy7c1471v33 byte a byte b byte d byte c a a
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 5 of 29 pin configurations (continued) 100-lead tqfp a a a a a1 a0 nc / 288m nc / 144m v ss v dd a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode a cy7c1473v33 byte a byte b a a
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 6 of 29 pin configurations (continued) 165-ball fbga (3 chip enable with jtag) cy7c1471v33 (2m x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 nc a a adv/ld nc oe a nc / 144m v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss nc cy7c1473v33 (4m x 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc nc nc dqp b nc dq b ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 nc a a adv/ld a oe a nc / 144m v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a0 a v ss nc a a a a
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 7 of 29 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dqpg dqh dqh dqh dqh dqd dqd dqd dqd dqpd dqpc dqc dqc dqc dqc nc dqh dqh dqh dqh dqph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dqpf dqa dqa dqa dqa dqe dqe dqe dqe dqpa dqpb dqf dqf dqf dqf nc dqa dqa dqa dqa dqpe dqe dqe dqe dqe aa a a nc nc nc a anc a aa aa a a1 a0 a aa aa a nc nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc v dd nc oe ce 3 ce 1 ce 2 adv/ld we v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ssq v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 209-ball pbga cy7c1475v33 (1m 72)
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 8 of 29 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw a , bw b , bw c , bw d , bw e , bw f , bw g , bw h input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the dev ice for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 , and ce 3 to select/desel ect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/desel ect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected stat e, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. during normal operation, this pin can be connected to vss or left floating. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as output s, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp x are placed in a tri-state condition.the outputs are automatically tri- stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utili zed, this pin should be left unconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages.
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 9 of 29 functional overview the cy7c1471v33, cy7c1473v33 and cy7c1475v33 are synchronous flow-through burst srams designed specifically to eliminate wait states dur ing write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and 4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another oper ation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. burst read accesses the cy7c1471v33, cy7c1473v33 and cy7c1475v33 have an on-chip burst count er that allows th e user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap around when incre- mented sufficiently. a high input on adv/ld will increment the internal burst counter regard less of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regar dless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp x . on the next clock rise the data presented to dqs and dqp x (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the wr ite operation is controlled by bw x signals. the cy7c1471v33, cy7c1473v33 and cy7c1475v33 provides byte write capability that is described in the truth table. asserting the write enable input (we ) with the selected byte write select input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capabilit y has been included in order to greatly simplify read/modify/w rite sequences, which can be reduced to simple byte write operations. because the cy7c1471v33, cy7c1473v33 and cy7c1475v33 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp x inputs. doing so will tri-state the output drivers. as a safety precaution, dqs and dqp x are automati- cally tri-stated during the data portion of a write cycle, regardless of the state of oe . tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag -clock clock input to th e jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc - no connects . not internally connected to the die. 144m and 288m are address expansion pins and are not internally connected to the die. pin definitions (continued) name i/o description
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 10 of 29 burst write accesses the cy7c1471v33, cy7c1473v33, and cy7c1475v33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write opera- tions without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent cl ock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw x inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, da ta integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 150 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next x x x l h x x h l l->h tri-state write cycle (begin burst) external l h l l l l l x l l->h data in (d) notes: 2. x = ?don't care.? h = logic high, l = logic low. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 3. write is defined by bw x , and we . see truth table for read/write. 4. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 5. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with the clock rise. it is ma sked internally during write cycles. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the device is deselected, and dqs and dqp x = data when oe is active.
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 11 of 29 write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h - sleep mode none x x x h x x x x x x tri-state truth table for read/write [2, 3, 9] function (cy7c1471v33) we bw a bw b bw c bw d read hxxxx write no bytes written lhhhh write byte a ? (dq a and dqp a ) l lhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d ) lhhhl write all bytes l l l l l truth table for read/write [2, 3, 9] function (cy7c1473v33) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l truth table for read/write [2, 3, 9] function (cy7c1475v33) we bw x read hx write ? no bytes written l h write byte x ? (dq x and dqp x) ll write all bytes l all bw = l note: 9. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write will be done based on which byte write is active. truth table (continued) [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 12 of 29 ieee 1149.1 serial boundary scan (jtag) the cy7c1471v33, cy7c1473v33, and cy7c1475v33 incorporate a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. t hese functions from the ieee specification are excluded bec ause their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devic es using 1149.1 fully compliant taps. the tap operates using jedec-standard 3.3v or 2.5v i/o logic levels. the cy7c1471v33, cy7c1473v33, and cy7c1475v33 contain a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 13 of 29 instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instru ction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture set-up plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 14 of 29 possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing tap ac switching characteristics over the operating range [10, 11] parameter description min. max unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 10.t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11.test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 15 of 29 3.3v tap ac test conditions input pulse levels ................................................ v ss to 3.3v input rise and fall times ......... .......................................... 1 ns input timing referenc e levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply vo ltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels................................................. v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ...................................... 1.25v output reference levels .......... ...................................... 1.25v test load termination supply voltage ............................ 1.25v 2.5v tap ac output load equivalent t do 1.5v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < t a < +70c; v dd = 3.3v 0.165v unle ss otherwise noted) [12] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3v 2.4 v i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1471v33 (2mx36) cy7c1473v33 (4mx18) cy7c1475v33 (1mx72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) [13] 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 001001 001001 001 001 defines memory type and architecture bus width/density(17:12) 100100 010100 110100 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 1 indicates the presence of an id register notes: 12. all voltages referenced to v ss (gnd). 13. bit #24 is ?1? in the id register definition s for both 2.5v and 3.3v ve rsions of this device.
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 16 of 29 scan register sizes register name bit size (x36) b it size (x18) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order?165fbga 71 52 - boundary scan order? 209bga - - 110 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. does not affect sram operation. this in struction does not implement 1149.1 preload function and is therefor e not 1149.1 compliant. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between td i and tdo. this operation does not affect sram operations.
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 17 of 29 boundary scan exit order (x36) bit # 165-ball id 1c1 2d1 3e1 4d2 5e2 6f1 7g1 8f2 9g2 10 j1 11 k1 12 l1 13 j2 14 m1 15 n1 16 k2 17 l2 18 m2 19 r1 20 r2 21 r3 22 p2 23 r4 24 p6 25 r6 26 n6 27 p11 28 r8 29 p3 30 p4 31 p8 32 p9 33 p10 34 r9 35 r10 36 r11 37 n11 38 m11 39 l11 40 m10 41 l10 42 k11 43 j11 44 k10 45 j10 46 h11 47 g11 48 f11 49 e11 50 d10 51 d11 52 c11 53 g10 54 f10 55 e10 56 a10 57 b10 58 a9 59 b9 60 a8 61 b8 62 a7 63 b7 64 b6 65 a6 66 b5 67 a5 68 a4 69 b4 70 b3 71 a3 72 a2 73 b2 boundary scan exit order (x36) (continued) bit # 165-ball id
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 18 of 29 boundary scan exit order (x18) bit # 165-ball id 1d2 2e2 3f2 4g2 5j1 6k1 7l1 8m1 9n1 10 r1 11 r2 12 r3 13 p2 14 r4 15 p6 16 r6 17 n6 18 p11 19 r8 20 p3 21 p4 22 p8 23 p9 24 p10 25 r9 26 r10 27 r11 28 m10 29 l10 30 k10 31 j10 32 h11 33 g11 34 f11 35 e11 36 d11 37 c11 38 a11 39 a10 40 b10 41 a9 42 b9 43 a8 44 b8 45 a7 46 b7 47 b6 48 a6 49 b5 50 a4 51 b3 52 a3 53 a2 54 b2 boundary scan exit order (x72) bit # 209-ball id 1a1 2a2 3b1 4b2 5c1 6c2 7d1 8d2 9e1 10 e2 11 f1 12 f2 13 g1 14 g2 15 h1 16 h2 17 j1 18 j2 19 l1 20 l2 21 m1 22 m2 23 n1 24 n2 25 p1 26 p2 27 r2 28 r1 29 t1 30 t2 31 u1 boundary scan exit order (x18) (continued) bit # 165-ball id
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 19 of 29 32 u2 33 v1 34 v2 35 w1 36 w2 37 t6 38 v3 39 v4 40 u4 41 w5 42 v6 43 w6 44 u3 45 u9 46 v5 47 u5 48 u6 49 w7 50 v7 51 u7 52 v8 53 v9 54 w11 55 w10 56 v11 57 v10 58 u11 59 u10 60 t11 61 t10 62 r11 63 r10 64 p11 65 p10 66 n11 67 n10 68 m11 69 m10 70 l11 71 l10 72 p6 73 j11 74 j10 75 h11 boundary scan exit order (x72) (continued) bit # 209-ball id 76 h10 77 g11 78 g10 79 f11 80 f10 81 e10 82 e11 83 d11 84 d10 85 c11 86 c10 87 b11 88 b10 89 a11 90 a10 91 a9 92 u8 93 a7 94 a5 95 a6 96 d6 97 b6 98 d7 99 k3 100 a8 101 b4 102 b3 103 c3 104 c4 105 c8 106 c9 107 b9 108 b8 109 a4 110 c6 111 b7 112 a3 boundary scan exit order (x72) (continued) bit # 209-ball id
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 20 of 29 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.5v to +4.6v dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd electrical characteristics over the operating range [14, 15] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage v ddq = 3.3v 3.135 v dd v v ddq = 2.5v 2.375 2.625 v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [14] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [14] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?5 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 5 a i oz output leakage current gnd v i v dd, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 335 ma 10-ns cycle, 100 mhz 305 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max , inputs switching 7.5-ns cycle, 133 mhz 200 ma 10-ns cycle, 100 mhz 200 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v dd ? 0.3v, f = 0, inputs static all speeds 150 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max , inputs switching 7.5-ns cycle, 133 mhz 200 ma 10-ns cycle, 100 mhz 200 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v , f = 0, inputs static all speeds 165 ma notes: 14. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 15. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 21 of 29 thermal resistance [16] parameter description test conditions 165 fbga typ. 209 bga typ. tqfp typ. unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 16.3 15.2 24.63 c/w jc thermal resistance (junction to case) 2.1 1.7 2.28 c/w capacitance [16] parameter description test conditions tqfp max. 209-bga max. 165-fbga max. unit c address address input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 6 6 6 pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c i/o input/output capacitance 5 5 5 pf ac test loads and waveforms note: 16. tested initially and after any design or process change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load 2.5v i/o test load
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 22 of 29 switching characteristics over the operating range [21, 22] parameter description 133 mhz 100 mhz unit min. max. min. max. t power? 1 1 ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.5 3.0 ns t cl clock low 2.5 3.0 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.5 2.5 ns t clz clock to low-z [18, 19, 20] 3.0 3.0 ns t chz clock to high-z [18, 19, 20] 3.8 4.5 ns t oev oe low to output valid 3.0 3.8 ns t oelz oe low to output low-z [18, 19, 20] 0 0 ns t oehz oe high to output high-z [18, 19, 20] 3.0 4.0 ns set-up times t as address set-up before clk rise 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 ns t wes we , bw x set-up before clk rise 1.5 1.5 ns t cens cen set-up befo re clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t ces chip enable set-up before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes: 17. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 18. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 19. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condi tion, but reflect parameters gua ranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions 20. this parameter is sampled and not 100% tested. 21. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 22. test conditions shown in (a) of ac test loads unless otherwise noted.
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 23 of 29 switching waveforms read/write waveforms [23, 24, 25] notes: 23. for this waveform zz is tied low. 24. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 25. order of the burst sequence is determined by the status of th e mode (0 = linear, 1 = interleaved). burst operations are opti onal. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6)
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 24 of 29 nop, stall and deselect cycles [23, 24, 26] note: 26. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a write is not performed during this cycle. switching waveforms (continued) write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6)
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 25 of 29 zz mode timing [27, 28] ordering information speed (mhz) ordering code package name part and package type operating range 133 cy7c1471v33-133axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) commercial cy7c1473v33-133axc cy7c1471v33-133bzc bb165c 165-ball fine-pitch ball grid array (15 x 17 x 1.4mm) cy7c1473v33-133bzc cy7c1475v33-133bgc bb209a 209-ball ball grid array (14 22 1.76 mm) cy7c1471v33-133bzxc bb165c lead-free 165-ball fine-pitch ball grid array (15 x 17 x 1.4mm) cy7c1473v33-133bzxc cy7c1475v33-133bgxc bb209a lead-free 209-ball ball grid array (14 22 1.76 mm) 100 cy7c1471v33-100axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) cy7c1473v33-100axc cy7c1471v33-100bzc bb165c 165-ball fine-pitch ball grid array (15 x 17 x 1.4mm) cy7c1473v33-100bzc cy7c1475v33-100bgc bb209a 209-ball ball grid array (14 22 1.76 mm) cy7c1471v33-100bzxc bb165c lead-free 165-ball fine-pitch ball grid array (15 x 17 x 1.4mm) cy7c1473v33-100bzxc cy7c1475v33-100bgxc bb209a lead-free 209-ball ball grid array (14 22 1.76 mm) please contact your local cypress sales repr esentative for availability of these parts. lead-free bg packages (ordering code: bgx) will be available in 2005. notes: 27. device must be deselected when entering zz mode. see truth ta ble for all possible signal conditions to deselect the device. 28. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 26 of 29 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 27 of 29 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.40 mm) bb165c 51-85165-*a
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *e page 28 of 29 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety a pplications, unless pursuant to an express written agreement with cypress. nobl and no bus latency are trademarks of cypress semiconduc tor corporation. zbt is a trademark of integrated device technology. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 209-ball fbga (14 x 22 x 1.76 mm) bb209a 51-85167-**
preliminary cy7c1471v3 3 cy7c1473v3 3 cy7c1475v3 3 document #: 38-05288 rev. *e page 29 of 29 document history page document title: cy7c1471v33/cy7c1473v 33/cy7c1475v33, 72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram with nobl? architecture document #: 38-05288 rev. *e rev. ecn no. issue date orig. of change description of change ** 114675 08/06/02 pks new data sheet *a 121521 02/07/03 cjm updated features for package offering updated ordering information changed advanced information to preliminary *b 223721 see ecn njy changed timing diagrams changed logic block diagrams modified functional description modified ?functional overview? section added boundary scan order for all packages included thermal numbers and capacitance values for all packages removed 150-mhz speed grade offering included isb and idd values changed package outline for 165fbga package and 209-ball bga package removed 119-bga package offering *c 235012 see ecn ryq minor change: the data sheets do not match on the spec system and external web. *d 243572 see ecn njy changed ball h2 from v dd to nc in the 165-ball fbga package in page 6 modified capacitance values on page 21 *e 299511 see ecn syt removed 117-mhz speed bin changed ja from 16.8 to 24.63 c/w and jc from 3.3 to 2.28 c/w for 100 tqfp package on page # 21 added lead-free information for 100-pin tqfp, 165 fbga and 209 bga packages added comment of ?lead-free bg packa ges availability? below the ordering information

▲Up To Search▲

Price & Availability of CY7C1471V33-133ACES

	To Download CY7C1471V33-133ACES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .